1. Field of the Invention
The present invention relates to an improved digital signal regeneration apparatus for regenerating digital signals recorded on a floppy disk, magnetic card, optical card, or other recording medium in MFM mode or 2-7 mode.
2. Description of the Related Art
Various digital signal recording/regenerating modes have been proposed in the past. To demodulate digital signals recorded on a recording medium correctly, measures must be taken against a variation in regenerated pulse duration due to a variation in relative moving rate between the recording medium and a read head, or a fluctuation in signal level or a missing signal due to flaws or dust on a medium.
Proposed, for example, in Japanese Patent Examined Publication No. 57-24700 is an analog mode based on a PLL mode which counts a phase difference between a regenerated pulse and a self-pulsing clock, and feeds back the count to the frequency of the self-pulsing clock wherein a read clock is produced to be synchronous with regenerated pulses, then used to demodulate regenerated pulses.
Alternatively, a digital mode uses a generated pulse as a reference to generate a read window signal for each pulse. For example, Japanese Patent Laid-Open No. 62-241176 has been proposed in which a clock bit cycle is extracted from a pulse spacing between regenerated pulses, a compensation clock whose reference cycle is half the extracted clock bit cycle is generated to form a read window signal, and thus regenerated pulses are demodulated.
The present applicant has proposed a digital signal regeneration apparatus is Japanese Patent Laid-Open No. 3-69069. In the digital signal regeneration apparatus, a reference cycle is calculated by averaging several pulse spacings detected during regeneration output, then a demodulation clock is generated to be synchronous with incoming pulses in the calculated clock cycles. This apparatus samples a data bit using a demodulating clock to determine whether demodulation data is 0 or 1.
As described previously, in Japanese Patent Examined Publication No. 57-24700, a phase difference between a regenerated pulse and a self-pulsing clock is fed back to the frequency of the self-pulsing clock, and thus a read clock is produced to be synchronous with regenerated pulses. Once a regenerated pulse and a read clock are out of phase, it takes too much time until the read clock becomes correctly in phase with a regenerated pulse. Moreover, an abrupt variation in pulse duration causes a phase lag. Consequently, the regenerated pulse is demodulated incorrectly. This makes it necessary to install a locking pattern formed with a regular signal train on a medium.
If sectors differ from each other greatly, synchronization may not be achieved. For example, if data is written in multiple sectors using difference equipment among the sectors, the signal interrecord gap may vary from sector to sector because of the differences among the equipment. In a recording mode in which sectors are not interspaced, especially, if sectors are read out consecutively, a synchronous out occurs at the transition from a sector to a succeeding sector. Consequently, data cannot be read from the subsequent sectors.
In Japanese Patent Laid-Open No. 62-241176, a clock bit cycle is extracted from a pulse spacing of an incoming pulse to form a demodulation window. In this case, since the clock cycle varies depending on an incoming pulse, when a pulse position changes drastically due to a fluctuation in moving rate of a medium, demodulation is done incorrectly. For example, when a pulse position shifts behind of a normal position, a pulse preceding the pulse becomes longer but a succeeding pulse becomes shorter. Therefore, if a clock cycle is extended with the preceding pulse, no pulse comes during a window open period. As a result, demodulation if done incorrectly. When a jitter (a distortion of a signal) occurs because of flaws or dust on a medium, if, for example, the pulse duration increases abruptly and the next pulse duration becomes shorter, bits overflow a data window. Specifically, clock bits and data bits are reversed, then demodulated.
In an apparatus according to Japanese Patent Laid-Open No. 3-69069, regenerated signal pulses are selectively synchronized in phase. Therefore, if a phase difference between a first incoming regenerated signal pulse and a clock is too great to achieve synchronization, since a generated clock tracks regenerated signal pulses moderately, the first regenerated signal pulse is not fully in phase with the clock. Furthermore, it takes much time to attain synchronization. Therefore, the apparatus described in the examined publication must have a synchronization pattern for locking on a recording medium in order to ensure precise locking from the beginning of regeneration and reduce the locking time.
Compared with an analog apparatus, the foregoing digital apparatus is good at achieving synchronization. However, when a pulse duration changes drastically from sector to sector, the digital apparatus, similarly to the analog apparatus, may fail to achieve synchronization. Consequently, a synchronous out occurs on a boundary between sectors and thereby subsequent data is not read out.